Nano Device Technologies

Modeling of TDDB in advanced Cu interconnect systems under BTS conditions

Due to the shrinking of the device size in integrated circuits together with the use of novel, less stable low-k back-end-of-line dielectrics more attention has to be paid to the time dependent dielectric breakdown (TDDB) effect. In this work the TDDB mechanisms are investigated and modeled based on constant-voltage bias-temperature stress (BTS) experiments from the 90 nm and 45 nm technology nodes. The modeling of the It dependencies is based on the numerical model of Haase in which it is assumed that the degradation of the dielectric is caused just by the electronic leakage current itself. By two simple modifications of the model and an adjustment of several model parameters it was possible to achieve a very good agreement between the model and the experiment for single constant-voltage BTS dependencies. For two different experimental data sets from the 45 nm technology node the TDDB behavior in dependence on the bias voltage and temperature is analyzed and compared with the results of the modified Haase model and the Poole–Frenkel lifetime model.