Packaging and (heterogeneous) integration (2D, 2.5D, 3D) for electronic devices

Micro and Nanoelectronics

Packaging and (heterogeneous) integration (2D, 2.5D, 3D) for electronic devices

This research and development area focuses on the development of processes for the integration of electronic devices for wafer level packaging, especially joining and contacting processes, thin film encapsulation and screen printing for metallization and solder.

Application examples and scenarios

 

Power packaging – silver and copper/tin sintering for power electronics

 

Tamper respondent envelope solutions realized by additive manufacturing – smart packaging solutions for secure applications

 

HyperConnect: self-assembly of micro and nanoparticles by centrifugal forces and capillary bridging for 3D thermal interconnects

 

Cool PoD: printed 3D chip-2-board interconnects

 

Materials and technologies to enable high-temperature stable MEMS and electronics