Processes and technologies for micro and nanoelectronics with the focus on back-end of line and interconnects
The development of individual processes (metal ALD, CVD, ULK processes, dry etching), novel concepts for diffusion barriers and alternative interconnect architectures for the reduction of parasitic effects (air gaps, alternative ULK integration) are the main focus of this topic.
Modeling and simulation of technological processes, equipment and devices
Experimental developments are supported by the simulation of processes (PVD, CVD, ALD, ECD), equipment and devices. Furthermore, device simulation and modeling of CMOS and nano devices (i.e. CNT FETs) as well as blackbox modeling and event-driven modeling and simulation are realized.
Beyond CMOS and RF devices, integrated circuits and technologies
This topic comprises developments of RF MEMS switches, CNT FETs as well as memristive devices and circuits.
Packaging and (heterogeneous) integration (2D, 2.5D, 3D) for electronic devices
This research and development area focuses on the development of processes for the integration of electronic devices for wafer-level packaging, especially joining and contacting processes, thin film encapsulation and screen printing for metallization and solder.
Electromagnetic and thermomechanic characterization and reliability evaluation
This topic addresses back-end of line components, chip-package interaction and reliability assessment of board and system level. Both, the thermomechanical reliability analysis and optimal layout for electronic components, devices and systems and simulative thermoelectrical reliability on a system (PCB) and package level, are addressed.