3D/MEMS Packaging

Business Unit » Process, Device and Packaging Technologies«

Fraunhofer ENAS is a leading research institute for the integration and reliability assessment of micro- and nanoelectronic systems. In the field of “3D/MEMS Packaging”, packaging and interconnect technologies for MEMS/NEMS, power and sensor modules, and hybrid 3D integration solutions are developed and tested in chip-, wafer-, component-, and system-level packaging. The portfolio ranges from classical assembly and interconnection techniques through additive printing methods and comprehensive characterization and reliability analysis − with particular expertise for demanding applications in harsh environments, power electronics, chiplet architectures and biocompatible microsystems. The entire spectrum of “System Packaging” across all major integration levels of micro- and nanoelectronic systems is covered − from the chip and wafer level through the package to the system- or board-level.

At the lowest integration level, work focuses on wafer-level processes and materials science fundamentals. This includes wafer and die-to-wafer bonding processes for MEMS, sensors or 3D chip stacks as well as the deposition of bonding interlayers and the development of pretreatment processes. In addition, layer deposition technologies are used to create conductor structures and functional layers directly on wafer or chip surfaces.

At the package level, the focus is on assembly and interconnection technologies. Fraunhofer ENAS develops and tests processes such as flip-chip bonding, wire bonding, chip-to-wafer, chip-to-chip, and multi-chip integration technologies in order to offer system-in-package solutions.

At the system- and board-level, work focuses on the development of hybrid microsystems as well as the integration of sensor, actuator, power and, communication electronics. 

Focus Areas of Research

 

Wafer-Level Packaging

Permanent or temporary joining methods for the connection of two or more wafers with and without intermediate layer

 

Chip-Level Packaging

Assembly of prefabricated and separated chips on substrates or composites.

System-Level Packaging

Assembly at component level as well as housings and thin film encapsulations

 

Layer Deposition

Thin film and thick film methods for deposition of materials onto various substrates

 

Interconnect

Mechanical and electrical interconnection technologies for semiconductor package 

 

Devices and MEMS

Research and development of smart systems such as ultrasound transducers 

 

Characterization

Destruction-free inspection (IR, SAM) | Microstructure analysis (REM, EDX, FIB) | Hermeticity | Strength

 

Parylene-based Packaging

Biocompatible thin film encapsulation using 3D conformal Parylene deposition

 

Equipment and Services

Client-oriented application of technologies and processes

 

3D Integration

Mechanical and electrical connects (TSV, TGV)