Reliability optimization of innovative design techniques of power electronic systems
In power electronics the replacement of the traditional interconnecting technologies becomes in particular a necessity when new wide bandgap semiconductors are introduced to manage the challenges of increasing power density, reliabilty and cost. A new interconnection technology based on wireless top side interconnects has been developed for compact inverter modules. Electrical connection is made by these structures, which provide additional heat spreading from top of the dies.
For the new interconnection technology, top side interconnects to the SiC semiconductors are made by metallic structured spacers to a leadframe. Parametric finite-element studies on the stress in dependence on spacer geometry and materials were made for temperature cycling. Different molding componds were analyzed. Additionally, effects of different spacer attach solders with standard lead-free solder properties, highly creep resistant Innolot properties, and high-temperature solder HT1 with creep compliant behavior have been compared.
Chip pad fatigue failure was observed to be one dominant failure mode. The evaluataion of this failure mode by standard FE methods is limited due to high pads aspect ratios and strongly non-linear materials behavior, in particular the aluminum pads and solder layers. Cohesive zone modeling (CZM) has been introduced to have a comparable damage metric. The methodology allows for modeling of the interface strength as well as the damage progress. By combined electro-thermal-mechanical modeling the overall transient temperature and stress fields are finally linked to the effects studied on local level.