Fraunhofer Institute for Electronic Nano Systems
Fraunhofer Institute for Electronic Nano Systems

Nano Device Technologies

Chemical Mechanical Polishing and Planarization (CMP)

Research and development topics

Fraunhofer ENAS Chemnitz has been working in the field of CMP technologies for several years. We address different kinds of CMP processes starting from metal polishing, especially copper and barrier materials, to silicon and silicon oxide processes. The applications connected to these processes range from back-end of line integration schemes in micro and nanoelectronics to the fabrication of specific substrates. Currently we have experiences in:

 

Silicon and silicon oxide CMP

  • MEMS-specific substrate fabrication
  • Fabrication of SOI substrates with buried silicides (SSOI) for advanced RF-devices
  • Surface activation for anodic and direct wafer bonding

 

Copper and barrier CMP

  • Silicon oxide based interconnect schemes
  • Dense and porous low-k based interconnect schemes
  • Air gap architectures

 

Consumable testing and evaluation

  • Slurry compatibility to low-k materials
  • Polishing pad testing
  • Performance evaluation (Removal rate, dishing, erosion)

Besides the aforementioned topics we offer customer specific process development from basic process setup to the final implementation. Furthermore, testing and evaluation of modified equipment parts, e.g. advanced polish heads, endorse our activities.

 

Equipment

Fraunhofer ENAS Chemnitz uses commercial tools like Applied Materials Mirra™ and IPEC 472 polishers as well as OnTrak DSS200 and G&P 428 scrubbers to ensure the necessary compatibility to our partners and customers. Besides that, table polisher and grinder from Logitech are available for basic and principle investigations.

 

Optimized Cu/barrier CMP for porous low-k dielectric based interconnects

Because of their lower mechanical stability and adhesion, porous low-k materials require a low down force polishing with optimized platen speed and slurry flow. For a porous MSQ based low-k stack a high number of defects were observed using a non-optimized Cu polish process. Cap layer or complete stack delamination were identified as failure mechanisms (shown in fig. 2).

Within a series of experiments slurry flow, platen speed, and down force were varied to figure out optimal settings. Applying these, no defects were found after polishing (shown in fig. 3).