Nano Device Technologies

Integration of low-k and ultra-low-k Dielectrics

Low-k dielectric materials have been developed for more than 10 years to replace SiO2 dielectrics and to lower parasitic capacitances between interconnect lines. The researchers at Fraunhofer ENAS and Center for Microtechnologies have long-term experience in developing processes and investigating integration aspects of ulta low-k (ULK) dielectrics (k ≤ 2.4) starting with mesoporous spin-on xerogels and CVD CF polymers already in 1998. Nowadays, the R&D efforts focus on integrating micro-porous SiCOH materials in leading edge CMOS technologies (45, 33, 28, 22 nm nodes).


The following processes and integration aspects are targeted:

  • damage-free etching processes
  • cleaning processes
  • resist stripping processes
  • CMP on low-k and ULK materials
  • interface between diffusion barriers and ULK dielectrics
  • pore sealing
  • simulation of breakdown behavior of porous dielectrics


Selected topics