Characterization of copper alloys for self-forming barrier applications
In copper wiring systems the barrier layer plays an important role. One major task of the layer is to prevent any Cu contamination of the dielectric. Recent researches focus on the self-forming barrier (SFB) approach. The main idea of SFBs is to replace the common Ta-based barrier with a copper alloy. The alloying element should form an ultrathin barrier layer at the interface to the SiO2 layer. However, the barrier formation requires a high-temperature step. In the CuDot project the elements Mn, Ti and Zr were investigated and compared to each other, in order to find the most suitable element for the SFB approach.
Integration scheme for self-forming barriers
The SFB integration scheme is displayed in figure 1. Basing on the dual damascene technology, the process starts with a patterned dielectric (a). A thin CuX alloy layer is deposited on top (b) and will be used as seed layer for the deposition of the copper bulk (c). Next, the barrier is formed (d). Therefore the wafer has to be heated up to a sufficient temperature. A high chemical gradient will attract the alloying element and an oxide or silicide layer will be formed. The subsequent CMP will remove the excessive Cu and any alloy-oxide on the surface (e). In comparison to the common integration scheme (f), the SFB is located only at the interface Cu/dielectric. This leads to a lower effective resistance especially in the vias.
We investigated Mn, Ti and Zr as alloying elements in the concentration range of 2 … 10 at. %. The alloys were deposited by co-sputtering. X-ray diffraction measurements show that all elements are deposited in a solid solution. Even CuZr is deposited in solution although these two elements are not miscible. This is a result of the high cooling rate during the sputtering. All three elements show a linear dependency of concentration to resistance. The CuZr system shows the highest values. During the annealing at 400 °C in N2/H2 ambient, the resistance reduces strongly. It can be shown that the Zr segregates and forms the Cu5Zr phase.
For the analysis of the barrier formation, we produced a layer stack of SiO2 (200 nm), alloy (50 nm) and pure Cu (500 nm). The wafers were annealed at 350 °C and 400 °C in N2/H2 atmosphere. Initially, the effective resistance of the layer stack was significantly higher than the value of a pure Cu layer. However, with the thermal annealing, we could reach values similar to pure Cu. Especially CuTi shows the best results. The barrier formation process has been investigated with tunneling electron microscopy (TEM) measurements. Figure 2 shows the as deposited state of an untreated layer stack. The alloy layer can clearly be separated from the pure Cu on top. Figure 3 shows a similar wafer after the annealing step. It can be shown, that each investigated element (Mn, Ti and Zr) will form an enrichment layer on the interface dielectric/alloy. This was proven by energy filtered TEM measurements, which show the element distribution in the analyzed area.
It is mandatory to prove the barrier stability of the new approach. Therefore, we produced MIS-testing structures which were tested with bias-temperature-stress (BTS) measurements and the triangular-voltage-sweep (TVS) method. It can be shown that a Zr SFB is less stable than a Mn or Ti SFB. Its leakage current is one magnitude higher than the other systems. A Ti-based barrier is slightly better than a Mn SFB.
We could show that all elements are capable to be used as SFB. Mn, Ti and Zr form an enrichment layer during the thermal annealing. Due to barrier stability and effective resistance, Ti seems to be the most suitable element for the SFB approach.
This work was supported by the EFRE fund of the European Community and by funding of the Free State of Saxony of the Federal Republic of Germany.
Special thanks to our project partner Infineon Technologies Dresden.