Fraunhofer Institute for Electronic Nano Systems
Fraunhofer Institute for Electronic Nano Systems

Simulation of Pulsed Electrochemical Copper Deposition in Through Silicon Vias with high Aspect Ratio

Business Unit » Process, Device and Packaging Technologies«

TSV model (gray, Ø 50 µm, depth 100 µm) with simulated copper surface (colored surface) after 3 h of unpulsed deposition with current density 0.4 A/dm².
© Fraunhofer ENAS
TSV model (gray, Ø 50 µm, depth 100 µm) with simulated copper surface (colored surface) after 3 h of unpulsed deposition with current density 0.4 A/dm².
Comparison of conventional unpulsed copper ECD without additives (a), with additives (b) and PRP ECD without additives (c).
© Fraunhofer ENAS
Comparison of conventional unpulsed copper ECD without additives (a), with additives (b) and PRP ECD without additives (c).

Through silicon vias (TSVs) are of key interest for 3D integration, enabling higher device densities and performances. The research goal of project VEProSi is a simplified process for the electrochemical deposition (ECD) of metals within TSVs.
Plating of TSVs with high aspect ratios is still challenging. Expensive and polluting chemicals (additives) are currently used to improve the uniformity of deposited metal layers. An alternative approach is periodic pulse reverse plating. This process was modeled at Fraunhofer ENAS, based on the Nernst-Planck equation, solved with the finite element method for a large number of combinations of pulse parameters.
It could be shown that the uniformity of deposited layers can be improved even without the use of additives. However, there is a tradeoff between process time and uniformity. From the simulation results, clear guidelines for optimal pulse plating processes are derived.