Low-k and even low-k (ULK) dielectric materials have been successfully developed with respect to their electrical properties. Numerous CVD or spin-on materials are available fulfilling the required permittivities. The integration of these materials in interconnect technology caused various challenges associated to process compatibility (sidewall damage, interface to barrier materials, pore sealing), thermal properties, mechanical (CMP, packaging) and chemical stability. Therefore the ITRS roadmap targets for interlevel metal insulator k-values (bulk/effective) have been softened annually. Airgap technologies, using air (k=1), as interlevel dielectrics, seem to be potential candidates for lowering the interlevel effective k-value and a simultaneous avoidance of integration issues, known especially from porous low-k materials. The different strategies for airgap formation, known from literature, can be allocated in two general techniques – void formation via non-conformal PECVD deposition and usage of sacrificial layers between metal lines.
In collaboration with TU Chemnitz two similar airgap technologies were developed. Both approaches, called “mask” and “spacer” approach are sacrificial layer methods and use sacrificial PECVD SiOx which is removed lateron by buffered HF wet etching. Controlled by additional patterned hard masks, they offer the opportunity of well defined etch attack, ensuring adequate mechanical and thermal properties. This is an appropriate basis for an application to multilevel metallization (especially successful CMP treatment) and sufficient reliability.
Structures of both approaches were characterized in terms of electrical, thermal and mechanical behaviour.
Effective permittivity (keff) of "mask" approach using 45 nm node "metal 1" geometries depending on thickness and k-value of all functional films