Back-End of Line

Back-End of line (BEOL) comprises the processing steps from contact level through to complete processing of the wafer prior to electrical testing, in other words, the entire interconnect system, including passivation. Ongoing downscaling has led to numerous diversifications over the past decade, depending largely on the product concerned. While transistors operate faster as their dimensions shrink, interconnects increasingly limit this gain in speed.

The resistance-capacitance product (RC product) of the interconnect system rises with reduced dimensions, and thus also the signal delay. Suitable materials can contribute to a resistance and capacitance decrease and therefore compensate for the performance loss in the interconnect system. The past decade was affected by the introduction of copper technology and low-k dielectrics. Further innovations and challenges are expected in the following years from the employment of ultra low-k dielectrics and the accompanying new processes required, such as ALD for ultra-thin films.

The department works in close collaboration with the Center for Microtechnologies at the TU Chemnitz on developing materials, processes and technologies for interconnect systems as well as on modeling and simulation of processes, equipment and interconnect systems. Special emphasis is placed on integrating low-k materials with material properties that require a modified integration pattern adapted to the respective material. Successful integration of the low-k materials is examined by means of electrical reliability assessments and analysis of long-term stability. New interconnect architectures continue to be developed, currently in particular airgaps. Here, not only the potential for manufacturing airgap structures is investigated, but also their electrical, thermal and mechanical impact on the interconnect system.

Developing new technologies requires new or optimized processes and equipment. To realize this, and to optimize existing processes, Fraunhofer ENAS is developing advanced models and simulation tools for PVD, CVD and CMP. It supports the development of improved deposition and polishing techniques by optimizing process conditions, reactor configuration, and feature topography.

The department collaborates with other institutes of the Fraunhofer Microelectronics Alliance, especially with the CNT, IISB and IZM.

 

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